1. Field of the Invention
The present invention relates to Peripheral Component Interconnect (PCI) devices and, more particularly, to a system and method for control of PCI memory read behavior when a disconnect occurs in mid data transfer between a master PCI device and a target PCI device.
2. Background Art
In a PCI system including a master that requests data from a memory storage device, the master does not necessarily communicate directly with the memory storage device. Typically, there is a bridge device between the master and the memory storage device. The bridge receives requests from the master on behalf of the memory, and may retry the master while it requests data from memory. The master may in fact be retried multiple times while the bridge is waiting for the data. When the bridge has obtained the data, and the master reissues its request, the bridge returns the data to the master. A request handled in this manner is referred to in PCI as a delayed request.
PCI read requests do not include length information, although some hints are provided through the fact that PCI includes several types of memory read commands. The only explicit information that the master can put in its request is that the master wants to receive at least one beat of data (e.g., 4 or 8 bytes) starting at a certain address. The bridge must make a determination of how much data to request from memory, based on the command used. If more than the initial beat of data is fetched from memory, that is referred to as prefetching, since the subsequent data beats have not actually yet been requested by the master. However, making assumptions as to the amount of data that the master is requesting raises certain issues. For example, if the bridge device reads more data than the master wants, system memory bandwidth is wasted since data is fetched that is not wanted. Furthermore, certain data is not prefetchable such as data that if read, is affected (e.g., a counter that increments when read). In this case, if data is read by the bridge device that is not requested by the master, the data may be destroyed. If the bridge initially reads less data than the master wants, it will run out of data when the reconnection occurs, forcing a disconnection (and possibly more retries) while it goes back to the memory for more data, again wasting PCI bus bandwidth and incurring extra latency.
The base memory read command in PCI is the Memory Read command. It conveys no length information beyond the first beat on the PCI bus and no prefetchability information. Accordingly, it is not possible in general for the bridge to safely prefetch. The bridge would therefore be expected to fetch data from memory 4 or 8 bytes at a time. When the master reconnects, the 4 or 8 bytes would be transferred and the bridge would then disconnect the transaction due to having no more data stored. If the master wants more than 4 or 8 bytes, it must reissue its request at the disconnected address, and the process must start over again. Hence, in this situation, performance is greatly limited since only 4 or 8 bytes of data are being received at a time.
The PCI Local Bus Specification Revision 2.3 dated Mar. 29, 2002 (hereinafter, the PCI Specification) defines, in addition to Memory Read, a Memory Read Line, and a Memory Read Multiple memory read command. Memory Read Line is used when reading more than 4 or 8 bytes such as an entire cacheline or up to an end of a cacheline. Memory Read Multiple is used when reading all or part of a first cacheline and at least one cacheline beyond the first cacheline.
Thus, as noted above, when a Memory Read command is used, a PCI target (e.g., bridge device) will generally obtain only the data that a master requested. The bridge device cannot read more because it does not know which bytes are required for the next data phase since that information is not available until the current data phase completes and the data may not be prefetchable. For Memory Read Line and Memory Read Multiple commands however, the master guarantees the address range is prefetchable; thus the bridge device can safely obtain more data than requested by the master, which is more efficient than Memory Read.
The bridge may be servicing delayed requests from several masters or several delayed requests from a single master at the same time. Accordingly, when the bridge receives a request, it must have a way to determine whether that request is a new request (which may need to be enqueued as a delayed request), or whether it is a reissue of a request that was previously retried or disconnected. This determination is made by comparing the command type, address, and (under some circumstances) byte enables of the stored request to the incoming request to see if they match.
When a master wants a large amount of data, and if the Memory Read Multiple command is used, the bridge device will fetch an amount of data. If the fetched amount of data is not as much as the amount of data the master wanted, the bridge will disconnect the data transfer when it runs out of data and the master will need to reissue the Memory Read Multiple command. If the bridge recognizes the reissued command as being part of the same transaction that was previously disconnected, and has had time to fetch more data from memory in the meantime, it will provide that data to the master. Since there was a disconnect and the master needs to reissue its request, it will be seeking a lesser amount of data because the bridge device already provided some data to the master.
The PCI Specification specifies which of the three read commands (mentioned above) a master may issue depending on the amount of data the master wants to receive. In the above example, since the master requires only a small amount of data, the master issues a Memory Read command instead of a Memory Read Multiple command. However, the bridge device has stored internally, the previous Memory Read Multiple command starting at a certain address. When the Memory Read is received, the address will match, but the command will not. Thus, the bridge device will treat the Memory Read command as a different request and will fetch the data over again increasing latency and wasting bandwidth both at memory and on the PCI bus. In addition, a buffer of the bridge contains the earlier Memory Read Multiple data that may need to be discarded. If the buffered data is not discarded and the same address is read later using a Memory Read Multiple command, the data may have gone stale or changed in memory. Thus, instead of the bridge device fetching data for the later Memory Read Multiple command, the bridge device may provide a master with stale data that associated with the earlier Memory Read Multiple command.
Hence, in certain PCI implementations, after a disconnect, there is a need for a bridge device to recognize a subsequent read request with a different command as a continuation of a previous read request. Furthermore, when dealing with a bridge device that is not able to recognize a different read command as a continuation, there is a need for a PCI master to be able to reissue the same command following a disconnect, even if the amount of data remaining to be requested in the reissued command is such that a different command would normally be appropriate.